A memory chip (such as, for example, a dynamic random access memory, DRAM, chip) will typically have a memory array region and a peripheral region proximate the memory array region. The memory array region is an area where densely-packed memory structures are formed as an array of individually-accessible memory devices, and the peripheral region will typically comprise less densely-packed circuitry utilized for accessing the circuitry of the memory array region. For instance, the peripheral region can comprise logic circuitry, and frequently will comprise complementary metal oxide semiconductor (CMOS) structures. CMOS structures contain n-channel and p-channel metal oxide semiconductor (MOS) transistors, and are frequently utilized for implementation of digital functions.
It is desired to utilize common semiconductor processing steps for fabrication of structures associated with the peripheral region simultaneously with fabrication of structures associated with the memory array region in order to decrease the amount of time utilized in fabricating a semiconductor construction and thereby increase throughput of a semiconductor fabrication process. However, it is also desired to optimize memory devices and peripheral devices for the particular applications of the devices, which can make it difficult to utilize common processing steps to simultaneously fabricate memory devices and peripheral devices.
The present invention was motivated, at least in part, by a desire to develop a processing method which can optimize aspects of peripheral devices, and yet utilize some common processing steps for simultaneous fabrication of memory device structures and peripheral device structures. It is to be understood, however, that even though the invention was motivated by such desire, the invention is not limited to such applications except to the extent, if any, that the applications are expressly recited in the claims that follow.